CLARO-CMOS, a very low power ASIC for fast photon counting with pixellated photodetectors

TL;DR

The paper presents CLARO-CMOS, a low-power ASIC designed for fast photon counting with pixellated photodetectors, achieving high speed, low noise, and excellent timing resolution in a 0.35 um CMOS technology.

Contribution

Introduction of CLARO-CMOS, a novel low-power, high-speed ASIC for photon counting, with improved timing resolution and efficiency for pixellated photodetectors.

Findings

Consumes less than 1 mW per channel at low rate

Achieves timing resolution down to 10 ps RMS

Recovery time less than 25 ns after each pulse

Abstract

The CLARO-CMOS is an application specific integrated circuit (ASIC) designed for fast photon counting with pixellated photodetectors such as multi-anode photomultiplier tubes (Ma-PMT), micro-channel plates (MCP), and silicon photomultipliers (SiPM). The first prototype has four channels, each with a charge sensitive amplifier with settable gain and a discriminator with settable threshold, providing fast hit information for each channel independently. The design was realized in a long-established, stable and inexpensive 0.35 um CMOS technology, and provides outstanding performance in terms of speed and power dissipation. The prototype consumes less than 1 mW per channel at low rate, and less than 2 mW at an event rate of 10 MHz per channel. The recovery time after each pulse is less than 25 ns for input signals within a factor of 10 above threshold. Input referred RMS noise is about 7.7 ke^- (1.2 fC) with an input capacitance of 3.3 pF. Thanks to the low noise and high speed, a timing resolution down to 10 ps RMS was measured for typical photomultiplier signals of a few million electrons, corresponding to the single photon response for these detectors.