Exploring performance and power properties of modern multicore chips via simple machine models

TL;DR

This paper combines performance modeling and power measurements to analyze multicore chip behavior, providing insights and guidelines for energy-efficient parallel computing on modern processors.

Contribution

It introduces a combined use of the ECM performance model and a simple power model to explain and predict multicore performance and power consumption behaviors.

Findings

ECM model predicts bandwidth-limited kernel scaling and saturation.

Power measurements enable a phenomenological power model for Sandy Bridge.

Models successfully describe and guide energy-efficient execution of a lattice-Boltzmann code.

Abstract

Modern multicore chips show complex behavior with respect to performance and power. Starting with the Intel Sandy Bridge processor, it has become possible to directly measure the power dissipation of a CPU chip and correlate this data with the performance properties of the running code. Going beyond a simple bottleneck analysis, we employ the recently published Execution-Cache-Memory (ECM) model to describe the single- and multi-core performance of streaming kernels. The model refines the well-known roofline model, since it can predict the scaling and the saturation behavior of bandwidth-limited loop kernels on a multicore chip. The saturation point is especially relevant for considerations of energy consumption. From power dissipation measurements of benchmark programs with vastly different requirements to the hardware, we derive a simple, phenomenological power model for the Sandy Bridge processor. Together with the ECM model, we are able to explain many peculiarities in the performance and power behavior of multicore processors, and derive guidelines for energy-efficient execution of parallel programs. Finally, we show that the ECM and power models can be successfully used to describe the scaling and power behavior of a lattice-Boltzmann flow solver code.