Space-Efficient Circuit Evaluation

TL;DR

This paper demonstrates that uniform circuits of size n can be evaluated in space O(n/log n), and extends the results to certain RAM models, showing space-efficient simulation of computational processes.

Contribution

It introduces a space-efficient evaluation method for uniform circuits and generalizes to RAM models with limited internal storage and read operations.

Findings

Uniform circuits of size n are evaluable in space O(n/log n)

Space(O(n)) is not in uniform Size o(n*log n)

Certain RAM models with limited reads can be simulated in space O(n log log n / log n)

Abstract

We prove that uniform circuits of size n can be evaluated in space O(n/log n). Thus, Space(O(n)) is not in uniform Size(o(n*log n)). For uniformity, we only require that the circuit is O(n/log n)-Space uniform. We also generalize the construction to prove that a machine with O(n^delta) (delta<1) internal storage and O(2^n^delta) length single-bit-access read-write RAM that does only O(n) RAM reads (1 bit per read) can be simulated in space O(n * log log n / log n).