The role of charge traps in inducing hysteresis: capacitance - voltage measurements on top gated bilayer graphene

TL;DR

This study investigates the hysteresis phenomenon in top gated bilayer graphene transistors, revealing that charge traps at the oxide-graphene interface are the primary cause, based on capacitance-voltage measurements.

Contribution

It provides new insights into the origin of hysteresis in graphene transistors, highlighting the role of charge traps at the interface through capacitance measurements.

Findings

Hysteresis exhibits a charging/discharging time constant of ~100 μs.

Capacitance across the graphene channel shows no hysteresis, only an abrupt jump at high voltage.

Charge traps in the gate oxide and interface are identified as the main cause of hysteresis.

Abstract

Understanding the origin of hysteresis in the channel resistance from top gated graphene transistors is important for transistor applications. Capacitance - voltage measurements across the gate oxide on top gated bilayer graphene show hysteresis with a charging and discharging time constant of ~100 {\mu}s. However, the measured capacitance across the graphene channel does not show any hysteresis, but shows an abrupt jump at a high channel voltage due to the emergence of an order, indicating that the origin of hysteresis between gate and source is due to charge traps present in the gate oxide and graphene interface.