Ethernet Packet Processor for SoC Application

TL;DR

This paper presents an Ethernet packet processor designed for SoC applications that enhances network performance by efficiently handling core packet functions and supporting high-speed links in FPGA implementations.

Contribution

The paper introduces a novel Ethernet packet processor architecture for SoC that integrates core packet functions and supports multiple high-speed network links.

Findings

Supports 10/100/1000 Mbps links with speed advantages

Implemented and simulated in FPGA using VHDL

Enhances switching and routing performance

Abstract

As the demand for Internet expands significantly in numbers of users, servers, IP addresses, switches and routers, the IP based network architecture must evolve and change. The design of domain specific processors that require high performance, low power and high degree of programmability is the bottleneck in many processor based applications. This paper describes the design of ethernet packet processor for system-on-chip (SoC) which performs all core packet processing functions, including segmentation and reassembly, packetization classification, route and queue management which will speedup switching/routing performance. Our design has been configured for use with multiple projects ttargeted to a commercial configurable logic device the system is designed to support 10/100/1000 links with a speed advantage. VHDL has been used to implement and simulated the required functions in FPGA.