The origin of gate hysteresis in p-type Si-doped AlGaAs/GaAs heterostructures

TL;DR

This study investigates the causes of gate hysteresis in p-type AlGaAs/GaAs heterostructures, revealing it is due to surface-state trapping and charge migration, and proposes methods to mitigate it for better device performance.

Contribution

The paper identifies the physical origins of gate hysteresis in p-type heterostructures and suggests practical mitigation strategies, challenging previous assumptions about gate leakiness.

Findings

Hysteresis is not caused by gate leakiness.

Surface-state trapping and charge migration are key factors.

Mitigation strategies include doping modifications and alternative gate materials.

Abstract

Gate instability/hysteresis in modulation-doped p-type AlGaAs/GaAs heterostructures impedes the development of nanoscale hole devices, which are of interest for topics from quantum computing to novel spin physics. We present an extended study conducted using custom-grown, matched modulation-doped n-type and p-type heterostructures, with/without insulated gates, aimed at understanding the origin of the hysteresis. We show the hysteresis is not due to the inherent `leakiness' of gates on p-type heterostructures, as commonly believed. Instead, hysteresis arises from a combination of GaAs surface-state trapping and charge migration in the doping layer. Our results provide insights into the physics of Si acceptors in AlGaAs/GaAs heterostructures, including widely-debated acceptor complexes such as Si-X. We propose methods for mitigating the gate hysteresis, including poisoning the modulation-doping layer with deep-trapping centers (e.g., by co-doping with transition metal species), and replacing the Schottky gates with degenerately-doped semiconductor gates to screen the conducting channel from GaAs surface-states.