Simulating Capacitances to Silicon Quantum Dots: Breakdown of the Parallel Plate Capacitor Model

TL;DR

This paper investigates the accuracy of simple models for predicting gate capacitances in silicon quantum dots, showing that while the parallel plate model works for larger devices, it fails for smaller ones due to fringing fields, and demonstrates a simulation approach for better predictions.

Contribution

The study quantifies the reproducibility of gate capacitances in silicon quantum dots and highlights the limitations of the parallel plate capacitor model for small devices, proposing a quick estimation method for fringing fields.

Findings

Gate capacitances are reproducible within 10% across devices.

Capacitance scales with device dimensions.

Parallel plate model fails for smallest devices due to fringing fields.

Abstract

Many electrical applications of quantum dots rely on capacitively coupled gates; therefore, to make reliable devices we need those gate capacitances to be predictable and reproducible. We demonstrate in silicon nanowire quantum dots that gate capacitances are reproducible to within 10% for nominally identical devices. We demonstrate the experimentally that gate capacitances scale with device dimensions. We also demonstrate that a capacitance simulator can be used to predict measured gate capacitances to within 20%. A simple parallel plate capacitor model can be used to predict how the capacitances change with device dimensions; however, the parallel plate capacitor model fails for the smallest devices because the capacitances are dominated by fringing fields. We show how the capacitances due to fringing fields can be quickly estimated.