Reduction of the small gain condition for large-scale interconnections
S. Dashkovskiy, M. Kosmykov

TL;DR
This paper introduces a method to simplify the verification of the small gain condition for large interconnected systems by aggregating subsystems based on motifs, reducing computational effort while ensuring input-to-state stability.
Contribution
The paper proposes heuristic aggregation rules based on motifs to reduce the complexity of verifying the small gain condition in large-scale systems, maintaining stability guarantees.
Findings
Aggregation preserves the main influence structure of the network.
Reduced small gain condition implies ISS of the entire network.
Application example demonstrates effectiveness of the approach.
Abstract
The small gain condition is sufficient for input-to-state stability (ISS) of interconnected systems. However, verification of the small gain condition requires large amount of computations in the case of a large size of the system. To facilitate this procedure we aggregate the subsystems and the gains between the subsystems that belong to certain interconnection patterns (motifs) using three heuristic rules. These rules are based on three motifs: sequentially connected nodes, nodes connected in parallel and almost disconnected subgraphs. Aggregation of these motifs keeps the main structure of the mutual influences between the subsystems in the network. Furthermore, fulfillment of the reduced small gain condition implies ISS of the large network. Thus such reduction allows to decrease the number of computations needed to verify the small gain condition. Finally, an ISS-Lyapunov function…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsControl and Stability of Dynamical Systems · Gene Regulatory Network Analysis · Low-power high-performance VLSI design
