Design and testing of high-speed interconnects for Superconducting multi-chip modules

TL;DR

This paper presents the design, optimization, and testing of high-speed superconducting interconnects for multi-chip modules, achieving near 100 GHz operation with minimal performance loss.

Contribution

It introduces optimized wideband interconnect designs for superconducting MCMs and evaluates key parameters affecting high-frequency performance.

Findings

Maximum operating frequency approaches 100 GHz

Interconnects cause only about 3% performance decrease

Optimized bump pad and micro-strip line design are crucial

Abstract

Superconducting single flux quantum (SFQ) circuits can process information at extremely high speeds, in the range of hundreds of GHz. SFQ circuits are based on Josephson junction cells for switching logic and ballistic transmission for transferring SFQ pulses. Multi-chip modules (MCM) are often used to implement larger complex designs, which cannot be fit onto a single chip. We have optimized the design of wideband interconnects for transferring signals and SFQ pulses between chips in flip-chip MCMs and evaluated the importance of several design parameters such as the geometry of bump pads on chips, length of passive micro-strip lines (MSL)s, number of corners in MSLs as well as flux trapping and fabrication effects on the operating margins of the MCMs. Several test circuits have been designed to evaluate the above mentioned features and fabricated in the framework of 4.5-kA/cm2 HYPRES process. The MCMs bumps for electrical connections have been deposited using the waferlevel electroplating process. We have found that, at the optimized configuration, the maximum operating frequency of the MCM test circuit, a ring oscillator with chip-to-chip connections, approaches 100 GHz and is not noticeably affected by the presence of MCM interconnects, decreasing only about 3% with respect to the same circuit with no inter-chip connections.