Proposal For Neuromorphic Hardware Using Spin Devices

TL;DR

This paper proposes a novel ultra-low power neuromorphic hardware design using spin devices, demonstrating significant energy efficiency improvements over traditional CMOS-based systems.

Contribution

It introduces a new device-model-based design scheme for spin-neurons and hybrid integration with CMOS, enabling energy-efficient neuromorphic architectures for various applications.

Findings

Achieves 15X-300X lower computation energy compared to CMOS designs.

Demonstrates versatile neuromorphic architectures for multiple applications.

Uses device-circuit co-simulation for performance evaluation.

Abstract

We present a design-scheme for ultra-low power neuromorphic hardware using emerging spin-devices. We propose device models for 'neuron', based on lateral spin valves and domain wall magnets that can operate at ultra-low terminal voltage of ~20 mV, resulting in small computation energy. Magnetic tunnel junctions are employed for interfacing the spin-neurons with charge-based devices like CMOS, for large-scale networks. Device-circuit co-simulation-framework is used for simulating such hybrid designs, in order to evaluate system-level performance. We present the design of different classes of neuromorphic architectures using the proposed scheme that can be suitable for different applications like, analog-data-sensing, data-conversion, cognitive-computing, associative memory, programmable-logic and analog and digital signal processing. We show that the spin-based neuromorphic designs can achieve 15X-300X lower computation energy for these applications; as compared to state of art CMOS designs.