FPGA-based Time to Digital Converter and Data Acquisition system for High Energy Tagger of KLOE-2 experiment

TL;DR

This paper presents an FPGA-based Time to Digital Converter and data acquisition system designed for high-precision timing measurements in the KLOE-2 experiment's High Energy Tagger, achieving sub-nanosecond resolution.

Contribution

The paper introduces a novel FPGA implementation of a TDC with 625 ps resolution and an integrated data acquisition system tailored for high-energy physics timing applications.

Findings

Achieved 625 ps timing resolution with FPGA-based TDC

Implemented efficient zero-suppression algorithm to reduce data throughput

Successfully integrated TDC with KLOE-2 online data acquisition system

Abstract

In order to reconstruct gamma-gamma physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2.7 ns). We have developed and implemented on a Xilinx Virtex-5 FPGA a Time to Digital Converter (TDC) with 625 ps resolution (LSB) along with an embedded data acquisition system and the interface to the online FARM of KLOE-2. We will describe briefly the architecture of the TDC and of the Data AcQuisition (DAQ) system. Some more details will be provided about the zero-suppression algorithm used to reduce the data throughput.