Design and implementation of real time AES-128 on real time operating system for multiple FPGA communication

TL;DR

This paper presents a real-time FPGA-based implementation of AES-128 encryption and decryption using RTOS to optimize speed and resource utilization, suitable for secure data communication systems.

Contribution

It introduces a hardware-software co-design of AES-128 on FPGA with RTOS, enhancing performance and efficiency over traditional implementations.

Findings

Successful implementation on Spartan-3E FPGA

Optimized for execution speed and hardware utilization

Demonstrates real-time encryption and decryption capabilities

Abstract

Security is the most important part in data communication system, where more randomization in secret keys increases the security as well as complexity of the cryptography algorithms. As a result in recent dates these algorithms are compensating with enormous memory spaces and large execution time on hardware platform. Field programmable gate arrays (FPGAs), provide one of the major alternative in hardware platform scenario due to its reconfiguration nature, low price and marketing speed. In FPGA based embedded system we can use embedded processor to execute particular algorithm with the inclusion of a real time operating System (RTOS), where threads may reduce resource utilization and time consumption. A process in the runtime is separated in different smaller tasks which are executed by the scheduler to meet the real time dead line using RTOS. In this paper we demonstrate the design and implementation of a 128-bit Advanced Encryption Standard (AES) both symmetric key encryption and decryption algorithm by developing suitable hardware and software design on Xilinx Spartan- 3E (XC3S500E-FG320) device using an Xilkernel RTOS, the implementation has been tested successfully The system is optimized in terms of execution speed and hardware utilization.