Microcontroller Based Testing of Digital IP-Core

TL;DR

This paper presents a cost-effective, flexible microcontroller-based testing methodology for digital IP-cores in SoC, eliminating the need for traditional test pattern generators and response analyzers, thus enabling at-speed testing with software-driven processes.

Contribution

The novel approach uses a microcontroller to perform both test pattern generation and response analysis, reducing cost and complexity in testing digital IP-cores.

Findings

Enables at-speed testing of IP-cores

Reduces testing cost and area overhead

Increases flexibility through software-based testing

Abstract

Testing core based System on Chip is a challenge for the test engineers. To test the complete SOC at one time with maximum fault coverage, test engineers prefer to test each IP-core separately. At speed testing using external testers is more expensive because of gigahertz processor. The purpose of this paper is to develop cost efficient and flexible test methodology for testing digital IP-cores . The prominent feature of the approach is to use microcontroller to test IP-core. The novel feature is that there is no need of test pattern generator and output response analyzer as microcontroller performs the function of both. This approach has various advantages such as at speed testing, low cost, less area overhead and greater flexibility since most of the testing process is based on software.