Wishbone bus Architecture - A Survey and Comparison

TL;DR

This paper surveys the WISHBONE bus architecture, comparing its performance and features with AMBA, CoreConnect, and Avalon, highlighting its advantages in flexibility, data transfer, and accessibility for SoC designs.

Contribution

It provides a comprehensive comparison of WISHBONE with other on-chip bus architectures, emphasizing its performance benefits and open availability.

Findings

WISHBONE offers flexible arbitration and extra data transfer cycles.

It has a performance edge over AMBA, CoreConnect, and Avalon.

WISHBONE cores are freely available without licensing restrictions.

Abstract

The performance of an on-chip interconnection architecture used for communication between IP cores depends on the efficiency of its bus architecture. Any bus architecture having advantages of faster bus clock speed, extra data transfer cycle, improved bus width and throughput is highly desirable for a low cost, reduced time-to-market and efficient System-on-Chip (SoC). This paper presents a survey of WISHBONE bus architecture and its comparison with three other on-chip bus architectures viz. Advanced Micro controller Bus Architecture (AMBA) by ARM, CoreConnect by IBM and Avalon by Altera. The WISHBONE Bus Architecture by Silicore Corporation appears to be gaining an upper edge over the other three bus architecture types because of its special performance parameters like the use of flexible arbitration scheme and additional data transfer cycle (Read-Modify-Write cycle). Moreover, its IP Cores are available free for use requiring neither any registration nor any agreement or license.