Mppsocgen: A framework for automatic generation of mppsoc architecture

TL;DR

This paper introduces MppSoCGEN, a framework that automates VHDL code generation for mppSoC architectures, streamlining design and validation processes for complex systems on Stratix II devices.

Contribution

It presents a novel design flow and tool for automatic VHDL code generation of mppSoC architectures based on architecture parameters and configuration rules.

Findings

Framework generates valid VHDL code efficiently.

Design flow reduces development time for mppSoC architectures.

Experimental validation confirms the effectiveness of the generated architectures.

Abstract

Automatic code generation is a standard method in software engineering since it improves the code consistency and reduces the overall development time. In this context, this paper presents a design flow for automatic VHDL code generation of mppSoC (massively parallel processing System-on-Chip) configuration. Indeed, depending on the application requirements, a framework of Netbeans Platform Software Tool named MppSoCGEN was developed in order to accelerate the design process of complex mppSoC. Starting from an architecture parameters design, VHDL code will be automatically generated using parsing method. Configuration rules are proposed to have a correct and valid VHDL syntax configuration. Finally, an automatic generation of Processor Elements and network topologies models of mppSoC architecture will be done for Stratix II device family. Our framework improves its flexibility on Netbeans 5.5 version and centrino duo Core 2GHz with 22 Kbytes and 3 seconds average runtime. Experimental results for reduction algorithm validate our MppSoCGEN design flow and demonstrate the efficiency of generated architectures.