Reversible Programmable Logic Array (RPLA) using Feynman & MUX Gates for Low Power Industrial Applications

TL;DR

This paper introduces a reversible programmable logic array (RPLA) design using Feynman and MUX gates implemented in VHDL, aiming for low power consumption in industrial applications.

Contribution

The paper proposes a novel RPLA design using Feynman and MUX gates with VHDL implementation, enhancing low power reversible logic circuit design.

Findings

VHDL codes for reversible gates are developed and simulated.

The proposed RPLA can implement various reversible and Boolean functions.

The design aims to reduce heat dissipation in logic circuits.

Abstract

This paper present the research work directed towards the design of reversible programmable logic array using very high speed integrated circuit hardware description language (VHDL). Reversible logic circuits have significant importance in bioinformatics, optical information processing, CMOS design etc. In this paper the authors propose the design of new RPLA using Feynman & MUX gate.VHDL based codes of reversible gates with simulating results are shown .This proposed RPLA may be further used to design any reversible logic function or Boolean function (Adder, subtractor etc.) which dissipate very low or ideally no heat.