Reduced-Complexity Column-Layered Decoding and Implementation for LDPC Codes
Zhiqiang Cui, Zhongfeng Wang, Xinmiao Zhang

TL;DR
This paper introduces a low-complexity, high-speed column-layered decoding scheme for LDPC codes, significantly reducing computational requirements and enabling multi-Gb/s throughput in VLSI implementations.
Contribution
It presents a novel low-complexity column-layered decoding algorithm with algorithmic transformations and a relaxed pipelining scheme for high-speed VLSI LDPC decoders.
Findings
Up to 90% reduction in check node processing complexity.
Achieved nearly 4 Gb/s decoding throughput with 10 iterations.
Developed a VLSI decoder in 0.13um CMOS for high-rate LDPC codes.
Abstract
Layered decoding is well appreciated in Low-Density Parity-Check (LDPC) decoder implementation since it can achieve effectively high decoding throughput with low computation complexity. This work, for the first time, addresses low complexity column-layered decoding schemes and VLSI architectures for multi-Gb/s applications. At first, the Min-Sum algorithm is incorporated into the column-layered decoding. Then algorithmic transformations and judicious approximations are explored to minimize the overall computation complexity. Compared to the original column-layered decoding, the new approach can reduce the computation complexity in check node processing for high-rate LDPC codes by up to 90% while maintaining the fast convergence speed of layered decoding. Furthermore, a relaxed pipelining scheme is presented to enable very high clock speed for VLSI implementation. Equipped with these new…
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Taxonomy
TopicsError Correcting Code Techniques · Advanced Wireless Communication Techniques · Cooperative Communication and Network Coding
