Three Dimensionial Surface Modelling: A Novel Analysis Technique for Non-Destructive X-Ray Diffraction Imaging of Semiconductor Die Warpage & Strain in Fully Encapsulated Integrated Circuits

TL;DR

This paper introduces a novel 3D surface modelling technique using X-ray diffraction to non-destructively map strain and warpage in fully encapsulated semiconductor IC packages with high resolution.

Contribution

The paper presents a new non-destructive X-ray based analysis method, 3DSM, capable of mapping deformation and strain in fully packaged ICs, filling a critical metrology gap.

Findings

High-resolution (~3 μm) strain and warpage maps obtained

Demonstrated on fully encapsulated IC packages from early to late manufacturing stages

Quantitative analysis of warpage in advanced packages

Abstract

Future complementary metal oxide semiconductor (CMOS) scaling for advanced integrated circuit (IC) technologies may well depend on "More than Moore" (MtM) approaches using heterogeneous integration of semiconductor-based devices. In order to realise this, advanced packaging technologies including System in Package (SiP), System on Chip (SoC) and 3D Integrated Circuits (3D ICs) are key enabling technologies. However, these advanced packages are plagued by reliability problems and to date there is no proven or accepted non-destructive metrology which can simultaneously probe materials properties such as strain, warpage, dislocation generation, etc. in these systems from bare silicon die through to a fully encapsulated packaged system. We report herein on the development of a novel, x-ray diffraction amd analysis technique, which can address this major metrology gap, and we demonstrate the non-destructive production of X-Y spatial maps of deformations and strain fields in Si die inside fully encapsulated integrated circuit packages. The technique, which we call 3-dimensional surface modelling (3DSM), is used to obtain high resolution (~3 {\mu}m) strain/warpage maps, and quantitative information on the nature and extent of warpage in a demonstration quad no flat lead (QFN) advanced package running from early stage silicon die bonding through to the end of the manufacturing process, i.e. a fully encapsulated and production ready chip.