Memory Hierarchy Sensitive Graph Layout
Amitabha Roy

TL;DR
This paper introduces a hierarchical blocking technique for graph layout that optimizes data placement across multiple memory hierarchy levels, significantly improving access times for large graphs.
Contribution
It presents a novel memory hierarchy-aware graph layout algorithm that extends hierarchical blocking to arbitrary graphs with minimal extra space.
Findings
Significant reduction in graph access times across various structures
Effective layout improvements for multiple memory hierarchy levels
Versatile implementation in C, C++ libraries, and JVM garbage collector
Abstract
Mining large graphs for information is becoming an increasingly important workload due to the plethora of graph structured data becoming available. An aspect of graph algorithms that has hitherto not received much interest is the effect of memory hierarchy on accesses. A typical system today has multiple levels in the memory hierarchy with differing units of locality; ranging across cache lines, TLB entries and DRAM pages. We postulate that it is possible to allocate graph structured data in main memory in a way as to improve the spatial locality of the data. Previous approaches to improving cache locality have focused only on a single unit of locality, either the cache line or virtual memory page. On the other hand cache oblivious algorithms can optimise layout for all levels of the memory hierarchy but unfortunately need to be specially designed for individual data structures. In this…
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Taxonomy
TopicsGraph Theory and Algorithms · Parallel Computing and Optimization Techniques · Advanced Graph Neural Networks
