Few Electron Limit of n-type Metal Oxide Semiconductor Single Electron Transistors

TL;DR

This paper demonstrates the fabrication and characterization of n-type silicon single electron transistors using CMOS technology, showing clear Coulomb blockade effects and modeling electron confinement with advanced theoretical methods.

Contribution

It presents a CMOS-compatible process for creating n-type silicon SETs with precise control, and provides detailed experimental and theoretical analysis of their electronic properties.

Findings

Coulomb blockade stability diagram resolved at 4.2 K

Large addition energies of tens of meV observed

Electron confinement modeled with CS-DFT

Abstract

We report electronic transport on n-type silicon Single Electron Transistors (SETs) fabricated in Complementary Metal Oxide Semiconductor (CMOS) technology. The n-MOSSETs are built within a pre-industrial Fully Depleted Silicon On Insulator (FDSOI) technology with a silicon thickness down to 10 nm on 200 mm wafers. The nominal channel size of 20 $\times$ 20 nm$^{2}$ is obtained by employing electron beam lithography for active and gate levels patterning. The Coulomb blockade stability diagram is precisely resolved at 4.2 K and it exhibits large addition energies of tens of meV. The confinement of the electrons in the quantum dot has been modeled by using a Current Spin Density Functional Theory (CS-DFT) method. CMOS technology enables massive production of SETs for ultimate nanoelectronics and quantum variables based devices.