High Speed, Low Power Current Comparators with Hysteresis

TL;DR

This paper introduces a high-speed, low-power analog current comparator with controllable hysteresis, utilizing current mirror and voltage latch techniques, suitable for 180nm CMOS technology.

Contribution

It presents a novel comparator design that achieves high speed and low power consumption with well-controlled hysteresis, extending to a hysteresis-free version for high accuracy.

Findings

Achieves high speed and low power operation

Provides well-controlled hysteresis in current comparison

Designs are optimized for 180nm CMOS process

Abstract

This paper, presents a novel idea for analog current comparison which compares input signal current and reference currents with high speed, low power and well controlled hysteresis. Proposed circuit is based on current mirror and voltage latching techniques which produces rail to rail output voltage as a result of current comparison. The same design can be extended to a simple current comparator without hysteresis (or very less hysteresis), where comparator gives high accuracy (less than 50nA) and speed at the cost of moderate power consumption. The comparators are designed optimally and studied at 180nm CMOS process technology for a supply voltage of 3V.