Design and modelling of different SRAM's based on CNTFET 32nm technology

TL;DR

This paper explores the design and modeling of SRAM memory cells based on 32nm CNTFET technology, demonstrating potential power efficiency improvements through simulations.

Contribution

It introduces novel SRAM designs utilizing CNTFETs at 32nm technology node, highlighting simulation-based performance and power advantages over traditional silicon-based SRAM.

Findings

Significant power savings in CNTFET-based SRAMs

Successful modeling and simulation using Stanford CNTFET model

Potential for high-density, low-power memory applications

Abstract

Carbon nanotube field-effect transistor (CNTFET) refers to a field-effect transistor that utilizes a single carbon nanotube or an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure. Since it was first demonstrated in 1998, there have been tremendous developments in CNTFETs, which promise for an alternative material to replace silicon in future electronics. Carbon nanotubes are promising materials for the nano-scale electron devices such as nanotube FETs for ultra-high density integrated circuits and quantum-effect devices for novel intelligent circuits, which are expected to bring a breakthrough in the present silicon technology. A Static Random Access Memory (SRAM) is designed to plug two needs: i) The SRAM provides as cache memory, communicating between central processing unit and Dynamic Random Access Memory (DRAM). ii) The SRAM technology act as driving force for low power application since SRAM is portable compared to DRAM, and SRAM doesn't require any refresh current. On the basis of acquired knowledge, we present different SRAM's designed for the conventional CNTFET. HSPICE simulations of this circuit using Stanford CNTFET model shows a great improvement in power saving.