Cross-point architecture for spin transfer torque magnetic random access memory

TL;DR

This paper introduces a cross-point architecture for STT-MRAM that significantly improves data density and addresses common issues like sneak currents and low speed, validated through simulation with realistic parameters.

Contribution

It proposes a novel cross-point design for STT-MRAM with shared transistors, enhancing density and addressing key circuit challenges with new techniques.

Findings

Data density improved to 1.75 F2/bit

Simulation shows competitive access speed and power consumption

Design effectively mitigates sneak current issues

Abstract

Spin transfer torque magnetic random access memory (STT-MRAM) is considered as one of the most promising candidates to build up a true universal memory thanks to its fast write/read speed, infinite endurance and non-volatility. However the conventional access architecture based on 1 transistor + 1 memory cell limits its storage density as the selection transistor should be large enough to ensure the write current higher than the critical current for the STT operation. This paper describes a design of cross-point architecture for STT-MRAM. The mean area per word corresponds to only two transistors, which are shared by a number of bits (e.g. 64). This leads to significant improvement of data density (e.g. 1.75 F2/bit). Special techniques are also presented to address the sneak currents and low speed issues of conventional cross-point architecture, which are difficult to surmount and few efficient design solutions have been reported in the literature. By using a STT-MRAM SPICE model including precise experimental parameters and STMicroelectronics 65 nm technology, some chip characteristic results such as cell area, data access speed and power have been calculated or simulated to demonstrate the expected performances of this new memory architecture.