A Resolution for Shared Memory Conflict in Multiprocessor System-on-a-Chip

TL;DR

This paper introduces a new semaphore scheme for shared cache memory synchronization in MPSoC, aiming to improve energy efficiency and reduce cache misses compared to traditional locks and transactional memory.

Contribution

It proposes a novel semaphore scheme specifically designed for shared cache memory in MPSoC systems, addressing synchronization challenges.

Findings

The new semaphore scheme reduces energy consumption compared to locks and transactions.

It achieves a lower cache miss rate in simulations.

The scheme outperforms traditional synchronization methods in embedded MPSoC environments.

Abstract

Now days, manufacturers are focusing on increasing the concurrency in multiprocessor system-on-a-chip (MPSoC) architecture instead of increasing clock speed, for embedded systems. Traditionally lock-based synchronization is provided to support concurrency; as managing locks can be very difficult and error prone. Transactional memories and lock based systems have been extensively used to provide synchronization between multiple processors [1] in general-purpose systems. It has been shown that locks have numerous shortcomings over transactional memory in terms of power consumption, ease of programming and performance. In this paper, we propose a new semaphore scheme for synchronization in shared cache memory in an MPSoC. Moreover, we have evaluated and compared our scheme with locks and transactions in terms of energy consumption and cache miss rate using SimpleScalar functional simulator.