Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate

TL;DR

This paper introduces a novel 3-transistor XNOR gate and a single-bit full adder using only 8 transistors, demonstrating improved power efficiency and performance through SPICE simulations in 0.35μm CMOS technology.

Contribution

A new 3-transistor XNOR gate and an 8-transistor full adder are proposed, reducing transistor count and power consumption compared to existing designs.

Findings

XNOR gate dissipates 550.7272μW at 3.3V

Full adder dissipates 581.542μW with improved voltage levels

Proposed circuits outperform previous designs in power and transistor count

Abstract

In present work a new XNOR gate using three transistors has been presented, which shows power dissipation of 550.7272$\mu$W in 0.35$\mu$m technology with supply voltage of 3.3V. Minimum level for high output of 2.05V and maximum level for low output of 0.084V have been obtained. A single bit full adder using eight transistors has been designed using proposed XNOR cell, which shows power dissipation of 581.542$\mu$W. Minimum level for high output of 1.97V and maximum level for low output of 0.24V is obtained for sum output signal. For carry signal maximum level for low output of 0.32V and minimum level for high output of 3.2V have been achieved. Simulations have been performed by using SPICE based on TSMC 0.35$\mu$m CMOS technology. Power consumption of proposed XNOR gate and full adder has been compared with earlier reported circuits and proposed circuit's shows better performance in terms of power consumption and transistor count.