The GANDALF 128-Channel Time-to-Digital Converter

TL;DR

The paper introduces a 128-channel time-to-digital converter (TDC) implemented in a single FPGA, achieving 64 ps resolution suitable for high-energy physics experiments, with detailed measurement results on its performance.

Contribution

It presents a novel FPGA-based 128-channel TDC design using shifted clock sampling, enabling high channel count with 64 ps resolution in a single FPGA.

Findings

Achieved 64 ps time resolution.

Demonstrated uniform routing and predictable placement within FPGA.

Provided measurement results for nonlinearity and accuracy.

Abstract

The GANDALF 6U-VME64x/VXS module has been designed to cope with a variety of readout tasks in high energy and nuclear physics experiments, in particular the COMPASS experiment at CERN. The exchangeable mezzanine cards allow for an employment of the system in very different applications such as analog-to-digital or time-to-digital conversions, coincidence matrix formation, fast pattern recognition or fast trigger generation. Based on this platform, we present a 128-channel TDC which is implemented in a single Xilinx Virtex-5 FPGA using a shifted clock sampling method. In this concept each input signal is continuously sampled by 16 flip-flops using equidistant phase-shifted clocks. Compared to previous FPGA designs, usually based on delay lines and comprising few TDC channels with resolutions in the order of 10 ps, our design permits the implementation of a large number of TDC channels with a resolution of 64 ps in a single FPGA. Predictable placement of logic components and uniform routing inside the FPGA fabric is a particular challenge of this design. We present measurement results for the time resolution and the nonlinearity of the TDC readout system.