The Efficiency of MapReduce in Parallel External Memory

TL;DR

This paper provides theoretical bounds on the I/O complexity of the MapReduce framework within the parallel external memory model, focusing on the shuffle step, and compares its efficiency to other models.

Contribution

It establishes upper and lower bounds for the shuffle step's I/O complexity in MapReduce, linking practical performance to theoretical models.

Findings

Matching upper and lower bounds for shuffle step I/O complexity

MapReduce's I/O efficiency can be bounded and compared to PEM and BSP models

Results show the potential performance loss in MapReduce relative to optimal algorithms

Abstract

Since its introduction in 2004, the MapReduce framework has become one of the standard approaches in massive distributed and parallel computation. In contrast to its intensive use in practise, theoretical footing is still limited and only little work has been done yet to put MapReduce on a par with the major computational models. Following pioneer work that relates the MapReduce framework with PRAM and BSP in their macroscopic structure, we focus on the functionality provided by the framework itself, considered in the parallel external memory model (PEM). In this, we present upper and lower bounds on the parallel I/O-complexity that are matching up to constant factors for the shuffle step. The shuffle step is the single communication phase where all information of one MapReduce invocation gets transferred from map workers to reduce workers. Hence, we move the focus towards the internal communication step in contrast to previous work. The results we obtain further carry over to the BSP* model. On the one hand, this shows how much complexity can be "hidden" for an algorithm expressed in MapReduce compared to PEM. On the other hand, our results bound the worst-case performance loss of the MapReduce approach in terms of I/O-efficiency.