FPGA implementation of a 32x32 autocorrelator array for analysis of fast image series

TL;DR

This paper presents a novel FPGA-based hardware implementation of a 32x32 autocorrelator array designed for real-time analysis of high-speed fluorescence imaging data from SPAD arrays, enabling efficient autocorrelation computations for dynamic cellular imaging.

Contribution

It introduces a new massively parallel multi-τ correlation hardware architecture optimized for FPGA, capable of real-time autocorrelation of high-speed image streams from SPAD arrays.

Findings

Calculates 1024 autocorrelation functions simultaneously.

Achieves 10μs temporal resolution in real-time processing.

Supports high-speed imaging with thousands of pixels.

Abstract

With the evolving technology in CMOS integration, new classes of 2D-imaging detectors have recently become available. In particular, single photon avalanche diode (SPAD) arrays allow detection of single photons at high acquisition rates (\geq 100 kfps), which is about two orders of magnitude higher than with currently available cameras. Here we demonstrate the use of a SPAD array for imaging fluorescence correlation spectroscopy (imFCS), a tool to create 2D maps of the dynamics of fluorescent molecules inside living cells. Time-dependent fluorescence fluctuations, due to fluorophores entering and leaving the observed pixels, are evaluated by means of autocorrelation analysis. The multi-{\tau} correlation algorithm is an appropriate choice, as it does not rely on the full data set to be held in memory. Thus, this algorithm can be efficiently implemented in custom logic. We describe a new implementation for massively parallel multi-{\tau} correlation hardware. Our current implementation can calculate 1024 correlation functions at a resolution of 10{\mu}s in real-time and therefore correlate real-time image streams from high speed single photon cameras with thousands of pixels.