Small Private Circuits

TL;DR

This paper introduces a new method for securing boolean and arithmetic circuits against wire-reading adversaries, achieving near-linear size increase and polylogarithmic security parameters, improving over previous quadratic solutions.

Contribution

The authors develop a circuit security method with size linear in s and polylogarithmic in t, utilizing DFT for efficiency, applicable to arithmetic circuits over arbitrary fields.

Findings

Achieved circuit size linear in s and polylogarithmic in t.

Utilized DFT to improve complexity from quadratic to quasilinear.

Applicable to arithmetic circuits over arbitrary fields.

Abstract

Ishai, Sahai, and Wagner initiated in 2003 the theoretical study of securing a circuit against an adversary who can probe its wires. They presented a universal way of transforming an arbitrary boolean circuit of size s into a circuit of size linear in s and quadratic in t, with perfect security against an adversary who can read up to t wires of the circuit. We present a new method for securing circuits against such an adversary with circuit size linear in s and polylogarithmic in t, while meeting the original privacy requirements from Ishai et al. Our solution works for arithmetic circuits over arbitrary fields of positive characteristic. The improvement from quadratic to quasilinear complexity (in t) comes from using the DFT instead of naive multiplication.