Hardware Implementation of Successive Cancellation Decoders for Polar Codes

TL;DR

This paper presents efficient hardware architectures for successive cancellation decoders of polar codes, achieving linear complexity and high throughput, with innovations in logarithmic domain implementation to reduce processing complexity.

Contribution

It introduces hardware designs for SC polar decoders with linear resource scaling and logarithmic domain processing, improving efficiency and implementation simplicity.

Findings

Decoders can be implemented with O(n) processing and memory elements.

Logarithmic domain implementation reduces processing complexity.

Hardware complexity grows linearly with code length.

Abstract

The recently-discovered polar codes are seen as a major breakthrough in coding theory; they provably achieve the theoretical capacity of discrete memoryless channels using the low complexity successive cancellation (SC) decoding algorithm. Motivated by recent developments in polar coding theory, we propose a family of efficient hardware implementations for SC polar decoders. We show that such decoders can be implemented with O(n) processing elements, O(n) memory elements, and can provide a constant throughput for a given target clock frequency. Furthermore, we show that SC decoding can be implemented in the logarithm domain, thereby eliminating costly multiplication and division operations and reducing the complexity of each processing element greatly. We also present a detailed architecture for an SC decoder and provide logic synthesis results confirming the linear growth in complexity of the decoder as the code length increases.