A general approach for high yield fabrication of CMOS compatible all semiconducting carbon nanotube field effect transistors

TL;DR

This paper presents a comprehensive method to achieve high-yield, CMOS-compatible carbon nanotube FETs by optimizing dielectrophoresis assembly parameters, resulting in record-high device yields and improved performance.

Contribution

The study introduces an optimized dielectrophoresis process for high-yield assembly of semiconducting carbon nanotubes, enabling scalable fabrication of high-performance FETs.

Findings

97% of devices show FET behavior with optimized parameters

Assembly yield reaches 90% with 90% FET demonstration

Achieved 100% assembly yield with up to 10 SWNTs per site

Abstract

We report strategies of achieving both high assembly yield of carbon nanotubes at selected position of the circuit via dielectrophoresis (DEP) and field effect transistor (FET) yield using semiconducting enriched single walled carbon nanotube (s-SWNT) aqueous solution. When the DEP parameters were optimized for the assembly of individual s-SWNT, 97% of the devices show FET behavior with a maximum mobility of 210 cm2/Vs, on-off current ratio ~ 106 and on conductance up to 3 {\mu}S, however with an assembly yield of only 33%. As the DEP parameters were optimized so that 1-5 s-SWNTs are connected per electrode pair, the assembly yield was almost 90% with ~ 90% of these assembled devices demonstrating FET behavior. Further optimization gives an assembly yield of 100% with up to 10 SWNT/site, however with a reduced FET yield of 59%. Improved FET performance including higher current on-off ratio and high switching speed were obtained by integrating a local Al2O3 gate to the device. Our 90% FET with 90% assembly yield is the highest reported so far for carbon nanotube devices. Our study provides a pathway which could become a general approach for the high yield fabrication of CMOS compatible carbon nanotube FETs.