Particle Swarm Optimization Framework for Low Power Testing of VLSI Circuits

TL;DR

This paper proposes a Particle Swarm Optimization framework to generate test vectors for VLSI circuits that achieve high fault coverage while minimizing power dissipation by reducing toggling during testing.

Contribution

It introduces a PSO-based method for optimizing test vector sequences to reduce power consumption in VLSI testing, improving efficiency over traditional genetic algorithms.

Findings

Reduces power dissipation during VLSI testing.

Achieves high fault coverage with minimized toggling.

Offers an efficient alternative to genetic algorithms.

Abstract

Power dissipation in sequential circuits is due to increased toggling count of Circuit under Test, which depends upon test vectors applied. If successive test vectors sequences have more toggling nature then it is sure that toggling rate of flip flops is higher. Higher toggling for flip flops results more power dissipation. To overcome this problem, one method is to use GA to have test vectors of high fault coverage in short interval, followed by Hamming distance management on test patterns. This approach is time consuming and needs more efforts. Another method which is purposed in this paper is a PSO based Frame Work to optimize power dissipation. Here target is to set the entire test vector in a frame for time period 'T', so that the frame consists of all those vectors strings which not only provide high fault coverage but also arrange vectors in frame to produce minimum toggling.