Low-Latency SC Decoder Architectures for Polar Codes

TL;DR

This paper introduces low-latency polar code decoders using look-ahead techniques and VLSI design methods, achieving 50% latency reduction while maintaining hardware efficiency for practical applications.

Contribution

The authors propose novel low-latency SC decoder architectures based on look-ahead techniques, recurrence properties, and hardware optimization strategies for polar codes.

Findings

Decoding latency reduced by 50% using look-ahead techniques.

Proposed architectures meet various application demands with hardware efficiency.

Detailed gate-level analysis confirms latency advantages over conventional designs.

Abstract

Nowadays polar codes are becoming one of the most favorable capacity achieving error correction codes for their low encoding and decoding complexity. However, due to the large code length required by practical applications, the few existing successive cancellation (SC) decoder implementations still suffer from not only the high hardware cost but also the long decoding latency. This paper presents novel several approaches to design low-latency decoders for polar codes based on look-ahead techniques. Look-ahead techniques can be employed to reschedule the decoding process of polar decoder in numerous approaches. However, among those approaches, only well-arranged ones can achieve good performance in terms of both latency and hardware complexity. By revealing the recurrence property of SC decoding chart, the authors succeed in reducing the decoding latency by 50% with look-ahead techniques. With the help of VLSI-DSP design techniques such as pipelining, folding, unfolding, and parallel processing, methodologies for four different polar decoder architectures have been proposed to meet various application demands. Sub-structure sharing scheme has been adopted to design the merged processing element (PE) for further hardware reduction. In addition, systematic methods for construction refined pipelining decoder (2nd design) and the input generating circuits (ICG) block have been given. Detailed gate-level analysis has demonstrated that the proposed designs show latency advantages over conventional ones with similar hardware cost.