Efficient Network for Non-Binary QC-LDPC Decoder

TL;DR

This paper introduces efficient network architectures for non-binary QC-LDPC decoders that significantly reduce memory and routing complexity by leveraging matrix properties, achieving over 70% reduction in hardware requirements.

Contribution

The paper proposes two novel network architectures for Class-I and Class-II non-binary QC-LDPC decoders, optimizing resource usage and enabling combined class support at low cost.

Findings

Over 70% hardware savings for Class-I code decoder

Over 93% shuffle network reduction for Class-II code decoder

Low-cost combined class decoder implementation

Abstract

This paper presents approaches to develop efficient network for non-binary quasi-cyclic LDPC (QC-LDPC) decoders. By exploiting the intrinsic shifting and symmetry properties of the check matrices, significant reduction of memory size and routing complexity can be achieved. Two different efficient network architectures for Class-I and Class-II non-binary QC-LDPC decoders have been proposed, respectively. Comparison results have shown that for the code of the 64-ary (1260, 630) rate-0.5 Class-I code, the proposed scheme can save more than 70.6% hardware required by shuffle network than the state-of-the-art designs. The proposed decoder example for the 32-ary (992, 496) rate-0.5 Class-II code can achieve a 93.8% shuffle network reduction compared with the conventional ones. Meanwhile, based on the similarity of Class-I and Class-II codes, similar shuffle network is further developed to incorporate both classes of codes at a very low cost.