FPGA implementation of short critical path CORDIC-based approximation of the eight-point DCT

TL;DR

This paper introduces a multiplierless eight-point DCT approximation using CORDIC algorithm optimized for FPGA, focusing on reducing critical path length and circuit delay.

Contribution

It presents a novel FPGA implementation of a short critical path CORDIC-based DCT approximation that minimizes combinational delay.

Findings

Reduced critical path length in FPGA implementation

Decreased combinational delay of the DCT circuit

Efficient multiplierless design for real-time processing

Abstract

This paper presents an efficient approach for multiplierless implementation for eight-point DCT approximation, which based on coordinate rotation digital computer (CORDIC) algorithm. The main design objective is to make critical path of corresponding circuits shorter and reduce the combinational delay of proposed scheme.