Generation of Test Vectors for Sequential Cell Verification

TL;DR

This paper presents a method to generate an optimized set of test vectors for verifying sequential cells in ASICs, ensuring complete transition coverage with minimal redundancy using simulation-based techniques.

Contribution

It introduces a novel approach that guarantees comprehensive transition coverage for sequential cell verification with minimal test vector redundancy, relying only on the cell's state table.

Findings

Achieves complete Single Input Change transition coverage.

Reduces the number of test vectors needed for verification.

Applicable to standard cell libraries in ASIC design.

Abstract

For Application Specific Integrated Circuits (ASIC) and System-on-Chip (SOC) designs, Cell - Based Design (CBD) is the most prevalent practice as it guarantees a shorter design cycle, minimizes errors and is easier to maintain. In modern ASIC design, standard cell methodology is practiced with sizable libraries of cells, each containing multiple implementations of the same logic functionality, in order to give the designer differing options based on area, speed or power consumption. For such library cells, thorough verification of functionality and timing is crucial for the overall success of the chip, as even a small error can prove fatal due to the repeated use of the cell in the design. Both formal and simulation based methods are being used in the industry for cell verification. We propose a method using the latter approach that generates an optimized set of test vectors for verification of sequential cells, which are guaranteed to give complete Single Input Change transition coverage with minimal redundancy. Knowledge of the cell functionality by means of the State Table is the only prerequisite of this procedure.