Accelerating Algorithms using a Dataflow Graph in a Reconfigurable System

TL;DR

This paper explores how implementing algorithms on a static dataflow architecture using FPGA can significantly boost computation speeds, demonstrating promising benchmark results.

Contribution

It introduces a static dataflow architecture on FPGA for algorithm acceleration, highlighting its potential for high computation rates.

Findings

High computation rates achieved in benchmarks

Effective implementation of static dataflow architecture

Potential for reconfigurable system acceleration

Abstract

In this paper, the acceleration of algorithms using a design of a field programmable gate array (FPGA) as a prototype of a static dataflow architecture is discussed. The static dataflow architecture using operators interconnected by parallel buses was implemented. Accelerating algorithms using a dataflow graph in a reconfigurable system shows the potential for high computation rates. The results of benchmarks implemented using the static dataflow architecture are reported at the end of this paper.