Optimal Final Carry Propagate Adder Design for Parallel Multipliers

TL;DR

This paper proposes optimal design expressions and adder configurations for the final carry propagate adder in parallel multipliers, optimizing delay, area, and power based on ASIC simulations.

Contribution

It introduces new expressions for adder region widths and specifies adder types for optimal hybrid final adder performance in parallel multipliers.

Findings

Optimal adder region widths derived from ASIC simulations

Hybrid adder configurations improve performance metrics

Design recommendations for 0.18 um CMOS technology

Abstract

Based on the ASIC layout level simulation of 7 types of adder structures each of four different sizes, i.e. a total of 28 adders, we propose expressions for the width of each of the three regions of the final Carry Propagate Adder (CPA) to be used in parallel multipliers. We also propose the types of adders to be used in each region that would lead to the optimal performance of the hybrid final adders in parallel multipliers. This work evaluates the complete performance of the analyzed designs in terms of delay, area, power through custom design and layout in 0.18 um CMOS process technology.