Faster Energy Efficient Dadda Based Baugh-Wooley Multipliers
B.Ramkumar, V.Sreedeep, Harish M Kittur

TL;DR
This paper introduces a faster, energy-efficient Dadda-based Baugh-Wooley multiplier using partitioning and hybrid addition techniques, achieving significant speed improvements with minimal power increase.
Contribution
It proposes a novel combination of partial product partitioning and hybrid adder design to enhance Baugh-Wooley multipliers' speed and efficiency.
Findings
64-bit multiplier is 26.9% faster
Power consumption increases by only 2.21%
Power-delay product is significantly reduced
Abstract
In this work faster Baugh-Wooley multiplication has been achieved by using a combination of two design techniques: partition of the partial products into two parts for independent parallel column compression and acceleration of the final addition using a hybrid adder proposed in this work. Based on the proposed techniques 8, 16, 32 and 64-bit Dadda based Baugh-Wooley multipliers has been developed and compared with the regular Baugh-Wooley multiplier. The performance of the proposed multiplier is analyzed by evaluating the delay, area and power, with 180 nm process technologies on interconnect and layout using industry standard design and layout tools. The result analysis shows that the 64-bit proposed multiplier is as much as 26.9% faster than the regular Baugh-Wooley multiplier and requires only 2.21% more power. Also the power-delay product of the proposed design is significantly…
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Taxonomy
TopicsLow-power high-performance VLSI design · Quantum-Dot Cellular Automata · Quantum Computing Algorithms and Architecture
