Using Genetic Algorithm in the Evolutionary Design of Sequential Logic Circuits

TL;DR

This paper presents a genetic algorithm-based method for designing and optimizing synchronous sequential logic circuits, reducing search space and the number of generations needed for evolution.

Contribution

It introduces a novel approach combining genetic algorithms with cell array-based logic synthesis for sequential circuits.

Findings

Reduced average number of generations in evolution

Effective search space limitation

Improved optimization of sequential circuits

Abstract

Evolvable hardware (EHW) is a set of techniques that are based on the idea of combining reconfiguration hardware systems with evolutionary algorithms. In other word, EHW has two sections; the reconfigurable hardware and evolutionary algorithm where the configurations are under the control of an evolutionary algorithm. This paper, suggests a method to design and optimize the synchronous sequential circuits. Genetic algorithm (GA) was applied as evolutionary algorithm. In this approach, for building input combinational logic circuit of each DFF, and also output combinational logic circuit, the cell arrays have been used. The obtained results show that our method can reduce the average number of generations by limitation the search space.