Implanted Bottom Gate for Epitaxial Graphene on Silicon Carbide

TL;DR

This paper introduces a buried electrostatic gate in silicon carbide to control epitaxial graphene's charge density, enabling device tuning while maintaining accessibility for further use, using standard semiconductor fabrication techniques.

Contribution

It presents a novel buried gate fabrication method for epitaxial graphene on silicon carbide, with detailed modeling of two gating regimes and temperature-dependent optimization.

Findings

Successful fabrication of tunable graphene devices with buried gates

Identification of two distinct gating regimes based on implantation parameters

Effective operation at both room and cryogenic temperatures

Abstract

We present a technique to tune the charge density of epitaxial graphene via an electrostatic gate that is buried in the silicon carbide substrate. The result is a device in which graphene remains accessible for further manipulation or investigation. Via nitrogen or phosphor implantation into a silicon carbide wafer and subsequent graphene growth, devices can routinely be fabricated using standard semiconductor technology. We have optimized samples for room temperature as well as for cryogenic temperature operation. Depending on implantation dose and temperature we operate in two gating regimes. In the first, the gating mechanism is similar to a MOSFET, the second is based on a tuned space charge region of the silicon carbide semiconductor. We present a detailed model that describes the two gating regimes and the transition in between.