On the Simulation of Time-Triggered Systems on a Chip with BIP

TL;DR

This paper introduces a BIP-based modeling approach for simulating Time-Triggered Systems on a Chip, enabling early validation of software components without requiring physical hardware.

Contribution

It presents functional models of TTSoC components in BIP, facilitating simulation and validation of software early in development.

Findings

Successful simulation of software components for TTSoC

Early validation without physical hardware

Demonstrated usability of BIP models

Abstract

In this report, we present functional models for software and hardware components of Time-Triggered Systems on a Chip (TTSoC). These are modeled in the asynchronous component based language BIP. We demonstrate the usability of our components for simulation of software which is developed for the TTSoC. Our software comprises services and an application part. Our approach allows us to simulate and validate aspects of the software system at an early stage in the development process and without the need to have the TTSoC hardware at hand.