Balanced ternary addition using a gated silicon nanowire

TL;DR

This paper demonstrates a proof of principle for a ternary adder using silicon single electron transistors, enabling inherently ternary operations with potential applications in low-power computing.

Contribution

It introduces a novel ternary addition method using silicon nanowire SETs, showcasing their capability for complex ternary logic operations.

Findings

Successful demonstration of ternary addition with silicon SETs

Robust three-valued output based on gate-dependent rectification

Potential for low-power, ternary logic circuits

Abstract

We demonstrate the proof of principle for a ternary adder using silicon metal-on-insulator single electron transistors (SET). Gate dependent rectifying behavior of a single electron transistor results in a robust three-valued output as a function of the potential of the SET island. Mapping logical, ternary inputs to the three gates controlling the potential of the SET island allows us to perform complex, inherently ternary operations, on a single transistor.