Modeling spin transport in electrostatically-gated lateral-channel silicon devices: role of interfacial spin relaxation

TL;DR

This study models spin transport in silicon devices with electrostatic gating, revealing that interfacial spin relaxation significantly reduces spin lifetime at the Si/SiO2 interface, influenced by extrinsic effects like paramagnetic defects.

Contribution

It introduces a finite-differences simulation approach to analyze interfacial spin relaxation effects in gated silicon devices, highlighting the role of extrinsic mechanisms.

Findings

Interfacial spin lifetime is about 1 ns, much lower than bulk silicon.

Spin relaxation at the top surface is negligible.

Extrinsic effects like paramagnetic defects contribute to spin relaxation.

Abstract

Using a two-dimensional finite-differences scheme to model spin transport in silicon devices with lateral geometry, we simulate the effects of spin relaxation at interfacial boundaries, i.e. the exposed top surface and at an electrostatically-controlled backgate with SiO_2 dielectric. These gate-voltage-dependent simulations are compared to previous experimental results and show that strong spin relaxation due to extrinsic effects yield an Si/SiO_2 interfacial spin lifetime of ~ 1ns, orders of magnitude lower than lifetimes in the bulk Si, whereas relaxation at the top surface plays no substantial role. Hall effect measurements on ballistically injected electrons gated in the transport channel yield the carrier mobility directly and suggest that this reduction in spin lifetime is only partially due to enhanced interfacial momentum scattering which induces random spin flips as in the Elliott effect. Therefore, other extrinsic mechanisms such as those caused by paramagnetic defects should also be considered in order to explain the dramatic enhancement in spin relaxation at the gate interface over bulk values.