Gate Bias Stress in Pentacene Field-Effect-Transistors: Charge Trapping in the Dielectric or Semiconductor

TL;DR

This paper investigates gate bias stress in organic field-effect transistors, identifying whether charge trapping occurs in the dielectric or semiconductor, and demonstrates how to produce devices immune to this instability.

Contribution

It distinguishes the roles of dielectric and semiconductor in charge trapping and shows how to fabricate OFETs resistant to gate bias stress.

Findings

Charge trapping can occur in the dielectric or semiconductor.

Devices with specific dielectric/semiconductor combinations can be immune.

Charge trapping mechanisms depend on material interfaces.

Abstract

Gate bias stress instability in organic field-effect transistors (OFETs) is a major conceptual and device issue. This effect manifests itself by an undesirable shift of the transfer characteristics and is associated with long term charge trapping. We study the role of the dielectric and the semiconductor separately by producing OFETs with the same semiconductor (pentacene) combined with different dielectrics (SiO$_2$ and Cytop). We show, it is possible to fabricate devices which are immune to gate bias stress. For other material combinations, charge trapping occurs in the semiconductor alone, or in the dielectric.