Process Optimization and Downscaling of a Single Electron Single Dot Memory

TL;DR

This paper details the process optimization and downscaling strategies for a single-electron nanoflash memory, emphasizing fabrication parameters and device size reduction to improve memory cell performance.

Contribution

It introduces a process modeling approach to optimize dot formation and demonstrates device downscaling by a factor of 2 based on scaling rules.

Findings

Optimized fabrication process for single-electron memory.

Confirmed device downscaling feasibility.

Identified key parameters influencing dot formation.

Abstract

This paper presents the process optimization of a single-electron nanoflash electron memory. Self-aligned single dot memory structures have been fabricated using a wet anisotropic oxidation of a silicon nanowire. One of the main issue was to clarify the process conditions for the dot formation. Based on the process modeling, the influence of various parameters (oxidation temperature, nanowire shape) has been investigated. The necessity of a sharp compromise between these different parameters to ensure the presence of the memory dot has been established. In order to propose an aggressive memory cell, the downscaling of the device has been carefully studied. Scaling rules show that the size of the original device could be reduced by a factor of 2. This point has been previously confirmed by the realization of single-electron memory devices.