Pseudo-Ring Testing Schemes and Algorithms of RAM Built-In and Embedded Self-Testing

TL;DR

This paper investigates pseudo-ring testing schemes for RAM and embedded memories, demonstrating their implementation with minimal additional logic and analyzing fault coverage, enabling at-speed testing for microcontrollers.

Contribution

It introduces pseudo-ring testing schemes for various memory types, detailing their implementation and fault coverage analysis, advancing self-testing methods for embedded systems.

Findings

Pseudo-ring schemes require minimal additional logic.

Effective at-speed testing of microcontrollers is achievable.

Fault coverage analysis shows promising results.

Abstract

Scan and ring schemes of the pseudo-ring memory selftesting are investigated. Both schemes are based on emulation of the linear or nonlinear feedback shift register by memory itself. Peculiarities of the pseudo-ring schemes implementation for multi-port and embedded memories, and for register file are described. It is shown that only small additional logic is required and allows microcontrollers at-speed testing. Also, in this article,are given the a posteriori values of some type of memories faults coverage when pseudo-ring testing schemes are applied.