Power Management during Scan Based Sequential Circuit Testing

TL;DR

This paper identifies power sensitive scan cells in scan-based testing and proposes a verilog-based method to freeze their outputs, significantly reducing power consumption during circuit testing.

Contribution

It introduces a novel approach to identify and freeze power sensitive scan cells, enhancing power efficiency in scan-based circuit testing.

Findings

Power sensitive scan cells cause more power during testing.

Freezing these cells reduces overall power consumption.

Multiple scan chains further improve power savings.

Abstract

This paper shows that not every scan cell contributes equally to the power consumption during scan based test. The transitions at some scan cells cause more toggles at the internal signal lines of a circuit than the transitions at other scan cells. Hence the transitions at these scan cells have a larger impact on the power consumption during test application. These scan cells are called power sensitive scan cells.A verilog based approach is proposed to identify a set of power sensitive scan cells. Additional hardware is added to freeze the outputs of power sensitive scan cells during scan shifting in order to reduce the shift power consumption.when multiple scan chain is incorporated along with freezing the power sensitive scan cell,over all power during testing can be reduced to a larger extend.