Enhancement-mode buried strained silicon channel quantum dot with tunable lateral geometry

TL;DR

This paper introduces a novel enhancement-mode SiGe/strained-Si quantum dot structure with tunable lateral geometry, demonstrating improved device performance and fabrication compatibility with standard silicon foundries.

Contribution

It presents a new relaxed-SiGe/strained-Si gate stack for quantum dots, achieving charge isolation and compatibility with existing fabrication processes.

Findings

Measured mobility of 1.6×10^5 cm^2/Vs at high carrier density

Observed periodic Coulomb blockade with open diamonds up to ±10 mV

Fabricated devices within a 150 mm Si foundry using standard processes

Abstract

We propose and demonstrate a relaxed-SiGe/strained-Si (SiGe/s-Si) enhancement-mode gate stack for quantum dots. The enhancement-mode SiGe/s-Si structure is pursued because it spaces the quantum dot away from charge and spin defect rich dielectric interfaces and minimizes background dopants. A mobility of 1.6\times10^5 cm^2/Vs at 5.8\times10^{11}/cm^2 is measured in Hall bars that witness the same device process flow as the quantum dot. Periodic Coulomb blockade (CB) is measured in a double-top-gated lateral quantum dot nanostructure. The CB terminates with open diamonds up to \pm 10 mV of DC voltage across the device. The devices were fabricated within a 150 mm Si foundry setting that uses implanted ohmics and chemical-vapor-deposited dielectrics, in contrast to previously demonstrated enhancement-mode SiGe/s-Si structures made with AuSb alloyed ohmics and atomic-layer-deposited dielectric. A modified implant, polysilicon formation and annealing conditions were utilized to minimize the thermal budget so that the buried s-Si layer would not be washed out by Ge/Si interdiffusion.