Device Improvement and Circuit Performance Evaluation of complete SiGe Double Gate Tunnel FETs

TL;DR

This paper conducts the first circuit-level analysis of extended channel double gate SiGe TFETs, evaluating their performance in digital circuits using compact models in Pspice, and compares them with MOSFETs.

Contribution

It introduces a novel circuit simulation approach for SiGe TFETs using compact models, enabling performance evaluation in digital circuits for the first time.

Findings

Extended channel SiGe TFETs show promising power-delay characteristics.

Device performance varies with Ge mole fraction and Si layer inclusion.

Compared to MOSFETs, TFETs offer potential advantages in low-power applications.

Abstract

In recent part extensive simulation work has already been done on TFETs. However this is limited to device performance analysis. Evaluation of circuit performance is a topic that is very little touched. This is due to the non availability of compact models of Tunnel FETs in the commercial simulator. In our paper for the first time we perform the circuit analysis of tunnel FETs (extended channel TFETs), we test them over basic digital circuit. We generate the TFET models by using the model editor in Orcad. Extensive circuit simulation is then performed by using these models in the Pspice circuit design. Performance of extended channel double gate TFET is evaluated on the grounds of power and delay in inverter, nand gate, nor gate and ring oscillator. Before that we perform device analysis of double gate extended channel TFETs, extended channel has been tried before on SOI TFETs we try it for the first time on double gate Si1-xGex TFETs. We even look at the effect of introducing Si layer. The performance of this device is compared for different Ge mole fraction and also with MOSFETs